The invention relates to a method for correcting the given duty cycle between the first time period of a first level state and the second time period of a second level state of at least a first periodic control/reference signal of a logic/memory unit to form a desired duty cycle.
For example, in order to process, transmit, store, etc. data signals, in digital systems, for example microprocessors, logic/memory modules such as DRAMs (Dynamic Random Access Memory), SDRAMs (Synchronous Dynamic Random Access Memory), or SGRAMs (Synchronous Graphic Random Access Memory), flash memories, integrated circuits such as ASICs, or in particular such circuits using CMOS technology, clocking is performed, i.e. the timing of switching times is determined, using at least one additional control/reference signal. Here, switchover times are defined by the given duty cycle between the time periods of the first and second level statexe2x80x94for example the high and low levelsxe2x80x94of such a periodic control/reference signal. Such a control/reference signal is usually referred to in microelectronics as a clock signal. In practice, the actual duty cycle between the time periods of the two level states of the period control/reference signal may then deviate from a desired setpoint duty cycle, in particular even fluctuate or vary chronologically with respect to it. However, as a result in particular clock-synchronous transmission, further processing and/or storage of data signals is made more difficult, as in the case of non-equidistant switching times partial superimposition of two successive data signals may occur. The chronological assignment of the individual data signals, which are each of preferably equal length, can thus become ambiguous at the switching times of the respective control/reference signal. In particular, as a result of such superimposition individual data bits are no longer reconstructed, no longer identified and are thus lost. When more stringent requirements are made of the processing speeds or data throughput rates, this problem becomes even more critical as, to solve it, a periodic control/reference signal with a relatively high frequency, i.e. shorter time intervals between its two different switching states, is used.
it is accordingly an object of the invention to provide a method and a logic/memory module for correcting the duty cycle of at least one control/reference signal that overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type and that corrects a desired setpoint duty cycle for at least one control/reference signal with at least two level states for the ratio of its time periods.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method in which the desired corrected duty cycle between the time periods of the first and second level states of the first control/reference signal is set in that the rising time period of its rising edge and/or the fall time period of its falling edge is increased and/or decreased by a predefinable correction time period.
A desired duty cycle between the time periods of the first and second level states of this clock/reference signal can easily and reliably be set in a controlled fashion by virtue of the fact that the rising time period of the rising edge and/or the fall time period of the falling edge of the respective control/reference signal is increased and/or decreased; thus, the rising edge and/or the falling edge of this control/reference signal is slowed down and/or sped up. The original level values for the first and second level states of the respective control/reference signal can thus be largely maintained as, of course, correction of the given duty cycle to form a desired setpoint duty cycle between the two level states of the respective control/reference signal is made possible only by using an active control of the edge rising time and/or edge fall time.
According to one expedient development of the invention, the duty cycle of the respective clock/reference signal is set in a correcting fashion such that the time period of its first level state corresponds essentially to the time period of its second level state. In other words, this means that expediently a 50:50 ratio is set between the time periods of the two level states of the respective control/reference signal. This 50 to 50 percentage duty cycle is referred to in microelectronics as a perfect duty cycle. This means in particular that during a clock cycle the digital high signal has as far as possible the same chronological length as the digital low signal. Such a 50% duty cycle is advantageous in particular for clock signals which use both the rising edge and the falling edge at each level change for triggering purposes, i.e. for clocking data signals such as, for example, for transmitting, further processing and/storing them. In this way, high-performance synchronous data transmissions can advantageously be carried out in a reliable way using two data bits per clock cycle, for example in a system with double data rate memory modules.
The invention also relates to a logic/memory module, in particular a double data rate memory module, which has at least one logic unit for carrying out the method according to the invention.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a logic/memory module for correcting the duty cycle of at least one control/reference signal, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.